//module name :demodTop
//module function : demod
//author:wataru
//2021.11.18
module demodTop(
		input clk,
		input rst,
		input signed [15:0]signalInDemod,
		output[15:0] rectificationResult,//整流结果数据，方便观察而添加的
		output [15:0] result //滤波结果
		

);
	reg[15:0] rectification_reg; 	//整流数据暂存
	wire[15:0] filter_in;			//滤波器输入信号
	reg[5:0] clkDivCnt;				//时钟分频计数器
	wire[34:0] filter_out_temp;   //滤波器输出缓存
	reg clk_1mhz_reg;//滤波器1MHZ时钟
	wire clk_1mhz;//滤波器1MHZ时钟
//-------------------------------
//div clk 1mhz,滤波器时钟模块
always@(posedge clk)begin
		if(rst)begin
			clkDivCnt <= 6'd0;
			clk_1mhz_reg <= 0;
		end
		else begin
			if(clkDivCnt == 6'd20)begin
				clk_1mhz_reg <= ~clk_1mhz_reg ;
				clkDivCnt <= 6'd0;
			end
			else begin
				clkDivCnt <= clkDivCnt + 1'b1;
				clk_1mhz_reg <= clk_1mhz_reg;
			end
		end
end
assign clk_1mhz = clk_1mhz_reg;
//全桥整流
always@(posedge clk ) begin
	if(rst)begin
		rectification_reg <= 16'd0;
	end//endIf1
	else begin
		if(signalInDemod[15] == 1)begin
			rectification_reg <= -{signalInDemod};
		end//endIf2
		else begin
			rectification_reg <= signalInDemod ;
		end//endElse2
	end//endElse1
end//alwaysEnd

assign rectificationResult = rectification_reg ;//finish the rectification


//filter 

assign  filter_in = rectification_reg ;
filter_50k_fs1mhz myfilter
               (
                .clk(clk_1mhz),
                .clk_enable(1'b1),
                .reset(rst),
                .filter_in(filter_in),
                .filter_out(filter_out_temp)//sfix35_En33
                );
assign result =  filter_out_temp[33:18];
endmodule//demodTop